The Aurora Protocol is a link layer communications protocol for use on point-to-point serial links. Developed by Xilinx, it is intended for use in high-speed (gigabits/second and more) connections internally between HIL computers or HIL connected to controllers or embedded systems.
 
OPAL -RT has been working on three different implementations of the Aurora protocol, as described in the following list:
  • Generic Aurora
  • Inter-FPGA communication
  • MMC communication over Aurora
 Generic Aurora

Aurora (8B10B) is a data-link layer protocol developed by Xilinx™ that is intended to be used for high speed communication. It uses 8b/10b encoding, which means that for every 8 bits of information to be sent, the protocol will send 10 bits. The encoding scheme allows for greater data integrity, but it also means that the theoretical maximum of 5 Gbps transfer rate is dropped down to 4 Gbps of useful data. 

  • The Aurora core is configured in “Framing” mode
  • Supports up to 16 High Speed SFP channels (one instance of the block per channel)
  • Various choices of data rates between 1 Gbps and 5 Gbps
  • MGT reference clock of 125 MHz or 250 MHz
  • Data and data validity are separate inputs to the block
Inter-FPGA Communication

This block is not application-specific. The inter-FPGA block transfers data from an FPGA to another; it can be used in all cases where a communication is required between two systems.

  • The Aurora core is configured in “Streaming” mode
  • Supports up to 16 High Speed SFP channels (one instance of the block per channel)
  • Data rate is fixed at 5 Gbps
  • MGT reference clock is fixed at 250 MHz
  • Supports between 1 and 32 data ports per channel (similar to dataIN and dataOUT blocks)
MMC Communication over Aurora

This block is application-specific. It is used for communication between a simulated MMC (Modular Multi-level Converter) and its hardware (or software) controller, which communicates over Aurora as well. Through out this protocol, it is possible to send up to 16bit for each cell with a minimum update rate of 5µs.

  • The Aurora core is configured in “Framing” mode.
  • Supports up to 16 High Speed SFP channels (one instance of the block per channel).
  • Various choices of data rates between 1 Gbps and 5 Gbps.
  • MGT reference clock of 125 MHz or 250 MHz.
  • Data and data validity are separated inputs to the block.
 
Performances

Achieved bandwidths:

100 MHz: the test was to feed the Aurora core with 513 DWORDs at every 520 clock cycles (5.2 µs) over a total time period of 161.2 µs, or 31 frames. Bandwidth achieved was 3.158 Gbps. Note that 513 DWORDs is the maximum quantity of data within a single frame.

200 MHz: the test was to feed the Aurora core with 300 DWORDs at every 500 clock cycles (2.5 µs) over a total time period of 82.5 µs, or 33 frames. Bandwidth achieved was 3.887 Gbps.

Note that the bandwidths that can be achieved also depend on the user clock (user backend application).

 
Supported modules

Compatible with OPAL-RT's cards: Kintex 7 and Virtex7 and OP7000

Provider: Xilinx