Jean Bélanger

Real-Time Digital Simulation and Control Laboratory for Distributed Power Electronic Generation and Distribution

Publication date : Nov 2005
Paper File : hsc2005.pdf



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Author(s)

Simon Abourida, Jean Bélanger, Christian Dufour,

Abstract

Complex power generation and distribution systems are needed on board spacecrafts, all electric warships, hybrid electric vehicles, distributed energy systems and other applications requiring compact, flexible autonomous energy generation systems. Several generators and complex active loads will be interconnected through power electronic distribution systems that must be designed to ensure voltage quality and system security under several normal and abnormal operating conditions.

Real-Time Closed-Loop Control of a 6-Pulse Rectifier with Switching-Event Compensation in Artemis

Publication date : Sep 2001
Paper File : app_ac_dc_converter.pdf



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Author(s)

Simon Abourida, Jean Bélanger, Christian Dufour,

Abstract

This short paper presents the results of testing ARTEMIS™ Advanced Real-Time Electro-Mechanical Transient Simulator on the simulation of a 6-pulse thyristor converter. The tests highlight the ARTEMIS Discrete-Time Compensation of Switching Events (DTCSE) and the RT-Events algorithms, showing that they yield faster and more precise fixed-time-step simulation of the power-system apparatus. This paper focuses on the open-loop characterization and the real-time closed-loop discrete control of a 6-pulse thyristor converter using the ARTEMIS DTCSE algorithm.

Real-Time and Hardware-in-the-Loop Simulation of Electric Drives and Power Electronics: Process, Problems and Solutions

Publication date : Apr 2005
Paper File : 2005_ipec_hil_elec.pdf



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Author(s)

Christian Dufour, Jean Bélanger, Simon Abourida,

Abstract

This paper discusses Real-Time and Hardware-In-The Loop simulation used for the design and testing of electric drives and power electronic systems. A thorough overview of the design process involving the approach of real-time simulation and rapid prototyping is given along with an explanation of the difficulties and pitfalls encountered, and the solutions available and implemented in RT-LAB real-time electrical engineering simulator.

PC-Cluster-Based Real-Time Simulation of an 8-synchronous machine network with HVDC link using RT-LAB and TestDrive

Publication date : Jun 2007
Paper File : 2007_ipst_dualkundurhvdc_dufour.pdf



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Author(s)

Vincent Lapointe, Loic Schoen, Jean-Nicolas Paquin, Jean Bélanger, Christian Dufour,

Abstract

In this paper, we detail the real-time simulation results of a medium-sized network composed of 8 synchronous machines and an HVDC link. The model is composed of two Kundur-like 4 machines networks connected together with a 12-pulse HVDC link. The complete network is modeled with SimPowerSystems with ARTEMIS real-time plug-in and is simulated in real-time on a RT-LAB InfiniBand PC-cluster composed of 3 dual-CPU dual-core Opteron PCs. The network model includes the HVDC control and protection systems as well as the synchronous machine regulators and power stabilizers. It also includes typical fault simulation capability like HVDC DC faults, thyristor misfires and AC faults. This model is excellent to study the complex interactions between an HVDC link and AC network under normal and transient conditions. The real-time simulation is controlled and monitored with a TestDrive interface from Opal-RT. This interface, based on LabView, permits easy monitoring and control of the complete system and enables Python-based scripting for automated tests. The proposed simulator can be interfaced with external equipments and controllers by direct reconfiguration of a FPGA I/O card with Xilinx System Generator blockset.

Modern Hardware-In-the-Loop Simulation Technology for Fuel Cell Hybrid Electric Vehicles

Publication date : Oct 2007
Paper File : vppc_paper_f.pdf



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Author(s)

Tetsuhiro Ishikawa, Simon Abourida, Jean Bélanger, Christian Dufour,

Abstract

This paper presents technologies designed for Hardware-In-the-Loop testing of modern motor drive systems commonly found in electric vehicles. Deliverable with the RT-LAB simulator comes various motor drive models with different precisions and complexities, from the basic Park two-axis machine models to detailed Finite-Element-Analysis based models. The former is more rapid while the latter is more precise. These models can be implemented on different hardwares, CPU or FPGA. CPU-based implementation rely on well-known ‘C’ code generation techniques and is rather flexible. FPGA implementation breaks through common limitations of CPU-based implementation by allowing much faster analog output rates, higher PWM frequencies and smaller model latencies. An FPGA implementation also allows the user to model fast protection schemes found on commercial drives (ex: over-current protections).

InfiniBand-Based Real-Time Simulation of HVDC, STATCOM and SVC Devices with Custom-Of-The-Shelf PCs and FPGAs

Publication date : May 2006
Paper File : hvdc_scv_isie06_final_paper.pdf



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Author(s)

Simon Abourida, Jean Bélanger, Christian Dufour,

Abstract

This paper presents a real-time simulator for large power network based on Custom-Of-The-Shelf technologies, all embedded in the RT-LAB real-time simulation platform. This platform uses Pentium, Xeon, Opteron-based PCs (multi-CPUs and/or dual-core configurations) or even Xilinx FPGA cards for computational engines and InfiniBand communication fabric for fast inter-PCs communications. The real-time PCs runs under well-known operating systems QNX or RedHawk Linux while the main user control interface is either Simulink or LabView. The paper demonstrates the real-time simulation of complete single-pole 12-pulse HVDC system on dual-CPU, dual-core 2.2 GHz Opteron PC under 15 microseconds time step. It also demonstrates the real-time simulation of complex power system devices like SVC, STATCOM and more general power systems like the Kundur network.

Hardware-In-the-Loop Simulation of Power Drives with RT-LAB

Publication date : Dec 2005
Paper File : peds2005_paper.pdf



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Author(s)

Jean Bélanger, Simon Abourida, Christian Dufour,

Abstract

This paper presents the RT-LAB Electrical Drive Simulator technology along with practical applications. The RT-LAB simulation software enables the parallel simulation of power drives and electric circuits on clusters of PC running QNX or RT-Linux operating systems at sample time below 10 μs. Using standard Simulink models including SimPowerSystems models, RT-LAB build computation and communication tasks necessary to make parallel simulation of electrical systems with standard off-the-shelf PCs and communication links like InfiniBand. To accommodate the high bandwidth of electrical systems, the RT-LAB Electrical Drive Simulator comes with special Simulink-based modeling tools, namely ARTEMIS and RT-Events that permits real-time simulation of electrical systems at practical time step of 10 μs but with sub-μs equivalent precision through the use of interpolation techniques. For power drives with even higher bandwidth, RT-LAB XSG permits simulation of PMSM drive at 1 μs on FPGA with VHDL code generated from Xilinx System Generator.

Hardware-In-the-Loop Simulation of Finite-Element Based Motor Drives with RT-LAB and JMAG

Publication date : May 2006
Paper File : hil_rtlab_jmag_paper_2006.pdf



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Author(s)

Tomoyuki Arasawa, Takashi Yamada, Simon Abourida, Jean Bélanger,

Abstract

This paper presents a new development in the field of design process and testing of motor drives, for hardware-in-the-loop (HIL) applications. It consists of implementing the Finite Element (FE) Method applied to electric motors on a real-time simulator; coupled with circuit simulation, this enables accurate real-time simulation of the complete motor drive, including the inverter and the motor. The paper describes the integration of FE-based motor model generated by JMAG® software, with the high-end real-time RT-LAB® simulator. The complete solution consists of combining accurate FE-based motor model, with inverter model, including important switching parameters, all constructed in the Simulink® environment, and simulated on PC-based RT-LAB simulation platform, using ultra-fast processors and FPGA-based inputs/outputs (I/O) boards. By connecting the real-time simulator to an external controller under test, this allows high fidelity HIL simulation of motor drives and enables the design engineers to test the system and the controller with a very accurate, FE-based motor model running in real-time.

FPGA-Based Real-Time Simulation of Finite-Element Analysis Permanent Magnet Synchronous Machine Drives

Publication date : Jun 2007
Paper File : 2007_pesc_fpga_jmag_dufour.pdf



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Author(s)

Simon Abourida, Jean Bélanger, Vincent Lapointe, Christian Dufour,

Abstract

This paper presents a real-time simulator of a permanent magnet synchronous motor (PMSM) drive based on a finite-element analysis (FEA) method and implemented on an FPGA card for HIL testing of motor drive controllers. The proposed PMSM model is a phase domain model with inductances and flux profiles computed from the JMAG-RT finite element analysis software. A 3-phase IGBT inverter drives the PMSM machine. Both models are implemented on an FPGA chip, with no VHDL coding, using the RT-LAB real-time simulation platform from Opal-RT and a Simulink blockset called Xilinx System Generator (XSG). The PMSM drive, along with an open-loop test source for the pulse width modulation, is coded for an FPGA card. The PMSM drive is completed with various encoder models (quadrature, Hall effects and resolver). The overall model compilation and simulation is entirely automated by RT-LAB. The drive is designed to run in a closed loop with a HIL-interfaced controller connected to the I/O of the real-time simulator. The PMSM drive model runs with an equivalent 10 nanosecond time step (100 MHz FPGA card) and has a latency of 300 ns (PMSM machine and inverter) with the exception of the FEA-computed inductance matrix routines which are updated in parallel on a CPU of the real-time simulator at a 40 us rate. The motor drive is directly connected to digital inputs and analog outputs with 1 microsecond settling time on the FPGA card and has a resulting total hardware-in-the-loop latency of 1.3 microseconds.

Electronic Platforms and On-Board Systems on Smart Vehicles: Dealing with Information in "Real-Time"

Publication date : Aug 2005
Paper File : autovision2010.pps



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Author(s)

Jean Bélanger,

Abstract

This presentation describes Opal-RT's next generation hardware-in-the-loop (HIL) tools to be used for the next generation vehicles. An in depth look at the challenges and solutions of developing testing strategies for electro/mechanical/hydraulic systems.

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