Wei Li

ANALYSIS AND HARDWARE-IN-THE-LOOP SIMULATION OF A POLE-TO-POLE DC FAULT IN MMC-BASED HVDC SYSTEMS

Publication date : Sep 2015
Paper File : COBEP_SPEC2015_MMC_v5.pdf



Share this document:

Author(s)

Authors: Weihua Wang, Jin Zhu, Wei Li, Jean Bélanger,

Abstract

This paper analyzes the possible range of the DC currents developed by a pole-to-pole DC fault in a Modular Multilevel Converter (MMC) -based high voltage direct current (HVDC) system, using half-bridge submodules (SM), when the actual control and protection (C&P) scheme for the system recently installed in China is applied. The results derived from differential equations are validated by hardware-in-the-loop (HIL) simulation with the complete C&P equipment. Unlike an AC fault at the grid side, which may be tested on a physical test bench or even on the actual system, a pole-to-pole DC fault is so severe that it can be only studied with a real-time digital simulator (RTS), if the dynamic response of the actual C&P system is involved.

Factory Acceptance Test of a Five-terminal MMC Control and Protection System using Hardware-in-the-loop Method

Publication date : Jul 2015
Paper File : Factory Acceptance Test of a Five-terminal MMC Control and Protection System using Hardware-in-the-loop Method.pdf



Share this document:

Author(s)

Yunlong Dong, Weihua Wang, Wei Li, OPAL-RT, NR Electric, Jie Tian, Jean Bélanger, Gang Li,

Abstract

Being the first five-terminal Modular Multilevel Converter (MMC)-based HVDC project in the world, the control and protection system must be validated under various operation modes as well as contingency at the factory acceptance test. This paper presents the configuration and performance of a hardware-in-the-loop (HIL) test platform that is based on a multi-rate real-time simulator using commercial-off-the-shelf architecture. The MMC sub-module model is implemented in field programmable gate array (FPGA) boards with a computation cycle of 500 ns, while the rest of the power system is simulated on the central processing unit (standard multi-core CPU) with a time-step of 30 μs. The State-space Nodal (SSN) interface is used to couple the models simulated on FPGA and on CPU. In addition, a communication protocol based on Giga-bit Ethernet is designed to connect the actual valve balancing controller with the real-time simulator. Results from the factory acceptance test are presented in this paper.

Setup and Performance of a Combined Hardware-in-loop and Software-In-Loop Test for MMC-HVDC Control and Protection System

Publication date : Jun 2015
Paper File : Final Paper MMC_ECCE Asia.pdf



Share this document:

Author(s)

Wei Li, Weihua Wang, Z hiyuanHe, Xueguang Wu, Dong Liu, Chang Lin,

Abstract

Despite the rapid development of VSC-HVDC technology, the practical experience to operate modular multi-level converter (MMC) has not yet been sufficiently accumulated. Real-time simulation is one of the most efficient approaches to verify the control and protection (C & P) scheme under various contingencies. With the increasing number of sub-modules, the accurate simulation of the MMC-HVDC becomes more difficult, as it requires larger computing resources and more complex interface between the test platform and the C&P system hardware devices. This paper proposes an application of real-time simulation, which combines the hardware-in--loop (HIL) and software-in-loop (SIL) approach to test a control and protection system for MMC-based HVDC links. In the proposed system, a pole control and protection (PCP) will be tested using the HIL approach, while the valve base controller (VBC) is tested using the SIL method. The setup of the test rig and performance is demonstrated in this paper.

Modular Multilevel Converters Over-Voltage Diagnosis and Remedial Strategy During Blocking Sequences

Publication date : Sep 2014
Paper File : Modular Multilevel Converters Over Voltage Diagnosis and Remedial Strategy During Blocking Sequences.pdf



Share this document:

Author(s)

Wei Li, Luc-André Gregoire, Lennart Ängquist, Kamal Al-Haddad, Handy Fortin Blanchette, Antonios Antonopoulos,

Abstract

In this paper the authors first highlight an existing over-voltage phenomenon that is inherent to the Modular Multilevel Converter (MMC) topology. The latter occurs during the blocking sequences of semiconductor devices if the converter needs to be stopped due to circulating current, loss of control or unexpected faults. An analysis based on time domain expressions describing each operating sequence during normal and faulty blocking conditions is used to demonstrate the origin of this over-voltage. Thereafter, system behavior is obtained when devices gating signals are withheld as well as the exact over-voltage cause. Real-time simulation, with sub-microsecond time-steps, and experimental results validate the over-voltage phenomena and the proposed remedial strategy to avoid uncontrolled faulty conditions.

Real-time simulation of a Modular Multilevel Back-to-back HVDC System using RT-LAB

Publication date : Sep 2014
Paper File : Not available yet

Share this document:

Author(s)

Weihua Wang, Jin Zhu, Wei Li, Yijun Zou,

Abstract

This paper demonstrates an advanced model based on the RT-LAB simulation platform, which is able to simulate a Modular Multilevel Back-to-back HVDC system for both steady-state operations and various contingencies in real time. This application takes advantages of the FPGA-based sub-microsecond model of the Modular Multilevel Converter (MMC) valves and combines it into the model of a Back-to-back HVDC link and adjacent AC networks using the State-space Nodal (SSN) solver. The real-time simulation is used to study the start-up and charging scheme, as well as the effectiveness of surge arrestors to mitigate the over-voltage of DC faults. Simulation results confirm the feasibility that the proposed model can be used to study the dynamic performance of Back-to-back MMC HVDC system.

Generic High Level VSC-HVDC Grid Controls and Test Systems for Offline and Real Time Simulation

Publication date : Aug 2014
Paper File : Generic High Level VSC-HVDC Grid Controls and test systems for offline and real time simulation.pdf



Share this document:

Author(s)

Wei Li, Student Member, Naveed Ahmad Khan, Md. Rokibul Hasan, Luigi VANFRETTI,

Abstract

This article describes generic high level control models for VSC-HVDC grid systems. An average value model of the voltage source converter (VSC) is used; it includes the vector current control strategy. As an improvement to traditional conventional high-level control systems, this paper includes dc voltage, negative sequence current and dc voltage droop control loops. To validate the controller’s performances, two tests systems were developed: a point-to-point link and a four-terminal DC grid. Both offline and real-time simulations are carried out for several test scenarios. A methodology for calibrating controller parameters is presented and used to tune the controls of each test system considering the different scenarios presented. All simulation models were developed in SimPowerSystem/Simulink and prepared using the RT-LAB software from OPAL-RT for real-time simulation; real-time simulation performance of the simulation models is also discussed

Modular Multilevel Converter Model Implemented in FPGA for HIL Test of Industrial Controllers

Publication date : Aug 2014
Paper File : Modular Multilevel Converter Model Implemented in FPGA for HIL Test of Industrial Controllers.pdf



Share this document:

Author(s)

Wei Li, Sisounthone Souvanlasy, Pierre-Yves Robert, Luc-André Gregoire, Jean Bélanger,

Abstract

Since Modular Multilevel Converters (MMC) have a sophisticated control, the real time simulation platform becomes critical for hardware-in-the-loop (HIL) test of the actual controllers in various scenarios before commissioning. This paper presents a multi-rate real time simulator that is able to simulate electromagnetic transients of MMC systems and connect to industrial controllers through fiber optics and copper wires for HIL tests. The MMC is implemented in field-programmable gate array (FPGA) with a sub-μs time step and the rest of the power system is simulated in the central processing unit (CPU) with a time step of 10~50 μs. Input and output (I/O) drivers are implemented in the same FPGA for a fast-rate and low-latency communication. Each FPGA accommodates up to 1530 sub-modules (SM), and multiple FPGA connected to one simulator can simulate MMC with more SM and multi-MMC systems. The performance is demonstrated in a 1500-SM MMC study case.

Modular-Multilevel-Converter Dynamic Analysis and Remedial Strategy for Voltage Transients During Blocking

Publication date : Sep 2013
Paper File : Modular Multilevel Converters Dynamic Analysis 2colones.pdf



Share this document:

Author(s)

Luc-André Gregoire, Handy Fortin Blanchette, Wei Li, Antonios Antonopoulos, Lennart Ängquist, Kamal Al-Haddad,

Abstract

This paper proposes a thorough analysis of the blocking sequence for modular multilevel converters in order to avoid fast voltage transients; such transients increase the stress on the different components of the converter. An issue was identified for this topology when blocking all the semiconductor devices. Under certain circumstances, unconditional blocking can result in an over-voltage on the dc bus, or across the inductors. The issue is studied using analytical equations and experimental results. A new controlled-blocking scheme is suggested in order to avoid this problem, and supporting real-time simulation results are provided.

Modeling and Control of a Full-Bridge Modular Multilevel STATCOM

Publication date : Feb 2012
Paper File : PES12_MMCSTATCOM.pdf



Share this document:

Author(s)

Jean Bélanger, Wei Li, Luc-André Gregoire,

Abstract

Due to its unique topology, the Modular Multilevel STATCOM has many advantages but requires a sophisticated controller and puts higher requirements on simulation tools. To simulate the STATCOM in real-time is preferable because it enables hardware-in-the-loop test of the system in various scenarios including extreme fault conditions, which cannot be tested on a real STATCOM. This paper presents a model of full-bridge sub-module which enables fast offline and real-time simulation of the STATCOM. A control scheme with a new SM capacitor voltage balancing method is also proposed in this paper. The model and the controller are investigated for different operating conditions. Implemented in a real-time simulator, the model can be simulated in real time at a time step of 20 µs, 131 times faster than its reference model. As demonstrated by the results, the proposed control scheme is effective and robust.

A Smart Distribution Grid Laboratory

Publication date : Nov 2011
Paper File : IECON2011_Smart_Distribution_Grid_Laboratory.pdf



Share this document:

Author(s)

Wei Li, Toshifumi Ise, Takeiki Aizono, Jean Bélanger, Isao Iyoda, Christian Dufour, Amine Yamane,

Abstract

This paper details a Smart Grid Laboratory for the study of modern house distribution systems with multiple energy sources and energy regeneration capability. The laboratory is designed to perform real-time simulation of a realistic distribution system connected to multiple houses. In addition, a real house with typical appliances and power sources is connected to the eMEGAsim real-time simulator with a Power- Hardware-In-the-Loop (PHIL) interface. Such PHIL interface enables the simulation of a simulated plant and real devices at a connection point where actual energy is exchanged between the two parts. Because of the coupling delays and the bandwidth of the plant and real devices, the stability of such a PHIL connection is not guaranteed. This paper will have a special emphasis on the stability of such power-HIL simulation.

Syndicate content