eDRIVEsim FAQ

FPGA development software

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Price will depend on:

The model time step specified (50 us or as low as 10 us)

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-  One perpetual license per processor core enabled
-  1 to 12 processor cores can be enabled per real-time computer target to minimize the total price;

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• Real-time target computer using server-grade standard motherboard equipped with the latest INTEL or AMD multi-core processors, whichever has the fastest debending at delivery time
  • Two hexa-core high-end 3.33 GHz CPUs per real-time computer target,
  • Very fast 12 Mbytes cache memory shared by all processor cores
  • Therefore, twelve (12)  3.33-Ghz CPU  per real-time computer target interfaced by , on-chip and onboard shared memory
• Up to 8 real-time computers can be interconnected using a very fast PCI Express switch (10 Gbits/s simultaneously)
  • Therefore 96 3.33-GHz processors can be interconnected
  • Each processor can communicate directly with any processor using shared-memory or the PCI Express switch
• I/O System
  • Each real-time computer can be connected to up to eight I/O systems (256 DIO or 128 analog channels and one FPGA per I/O system) using a PCI Express switch (40 Gbits/s)
  • The FPGA located on each I/O system can send and receive data by Direct Memory Transfer to and from each processor core without any intervention form the processor
  • Processor cores can make the model calculation while the I/O data are transferred to the FPGA I/O processors
  • each I/O system (FPGA plus analog converters and signal conditioning boards) can be installed remotely in manufacturer controller racks and interfaced to the real-time target computer with fiber optic links
• FPGA Programming
  • The FPGA I/O processor can be user-programmed using the SIMULINK and XILINX System Generator Tool to implement special custom models, controllers and protection algorithms or signal processing
  • FPGA codes are provided for standard I/O functions like PWM, time stamping...

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• Analog converter module with 16 independent 16-bit converter,
  • 2.5 us conversion time (16 ch. Converted in 2.5 us)
  • Optional converters with 500 nanoseconds conversion time available (16 channels Converted in 500 nanoseconds)
  • Front-end instrumentation differential amplifiers with maximum input voltage range adjustable from +_ 1V +- 100V (+- 600V optional attenuator box)  by changing two resistors to keep the full 16-bit resolution
  • Simultaneous conversion of all channels controlled by the FPGA
  • Possibility to control the coversion time of each channel by the FPGA
  • Possibility to convert analog signal between the base simulator time step to implement special models and signal processing functions with time step of 2.5 micros or 500 nanoseconds depending on A/D converter speed selected
  • Gain and offset calibration factor adjustable through software and stored on local non-volatile memory installed on the module
• Analog converter output module with 16 independent 16-bit converters,
  • One (1) us conversion time per converter (16 channels Converted in 1 us)
  • With output buffer amplifiers with maximum output voltage range adjustable from +_ 100 mV to +- 16 V  (+- 16 V standard)  to keep the full 16-bit resolution
  • Simultaneous conversion of all channels controlled by the FPGA
  • Possibility to control the conversion time of each channel by the FPGA
  • Possibility to convert analog signal between the base simulator time step to implement special models and signal processing functions with time step of 1 micros
  • Gain and offset calibration factor adjustable through software and stored on local non-volatile memory installed on the module
  • Short-circuit protection at 10 mA (optional 100 mA buffer available)
• Discrete output module with 32 independent channels per module
  • Push-pull type
  • 50 nanoseconds delay
  • Galvanic isolation
  • Output voltage adjustable from 5V to 30V
  • Short-circuit protection at 100 mA
• Optional TTL,  SPI and LVDS output
• Discrete Input module with 32 independent channels per module
  • Current input from 2 mA to 6 mA
  • Input current protection by a resettable solid-state fuse
  • Input voltage adjustable from 5V to 30 V
  • 100 nanoseconds delay maximum
  • Galvanic isolation
• Optional TTL,  SPI and LVDS digital input
• Optical fiber Input and output module with 32 independent channels per module
  • 10 Mbits optical interface
  • Type of optical interface selected for the specific application
• High-voltage Input and output module with 32 independent channel per module
  • 100-volt voltage output, 1 us, for the train industry
  • Source or sink mode
• 1-A, 10V current output  module with 8 independent channels per module
  • 50-kHz bandwidth
  • Used to interface with control systems with high-current input
• 5A to 50 A current sensor and +- 600 V voltage sensor  module
  • 4 current sensors and 4 differential voltage sensors per module
  • 50-kHz bandwidth
• Other Optional I/O boards
  • See the complete list of signal conditioning modules
  • See other I/O boards supported
  • See the list of FPGA boards and chips supported

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