How to define the Maximum number of cached switch pattern matrix permutations

Question: What kind of consideration should I take to define the Maximum number of cached switch pattern matrix permutations in ARTEMIS GUIDE BLOCK?

Answer: The Maximum number of cached switch patterns matrix permutations must be set GREATER than the number of topology of switch patterns that actually occur during the simulation. Otherwise, you will see continuous overruns come out throughout the simulation, since not all possible state-space matrices are stored in memory cache and recalculation of state-space matrices cause a large overhead.

Ideally, when you have N SPS switches (including circuit breakers, ideal switches, and other SPS power electronic swithces but excluding Time-stamped bridges)  in one single topologically connected network of your model, it requires 2^N cached switch pattern matrix permutations to hold the complete sets of state-space matrix. However, if you have many switches in the model, you would better to consider the actually possible number of patterns based on your control strategies to avoid overloading the RAM. For example, a standard 6-pulse rectifier has totally 7 possible switching patterns including the dead-time or natural rectification mode. 

Please also note that maximum number of SPS switch is 28 in a single topologicaly connected network even in Dynamic calculation. If you have more than 28 switches, you have to think about using TSBs to replace some SPS power electronic blocks, or using Artemis Lines (stub-line/Distributed Parameter Lines), Nodal Interface Blocks (NIB)- SSN method to decouple your networks.