ML506 - Integrated FPGA Development System
Enclosure and I/O Signal Conditioning for the ML506 Development Board. |
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Specifications
- ML506 Virtex5 Developement Board
- Two Type B mezzanines for Signal Conditioning (16 DAC or 16 ADC per mezannine)
- Up to 70 3.3V Buffered Digital I/O Line connected directly to Virtex5 FPGA
Operation Mode
- Stand Alone (FPGA Programming using JTag)
- HIL Mode (Connected to a Real-Time HIL Target usgin PCIx Communication Link)
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