OP5142 - Spartan3 FPGA Reconfigurable I/O Node

 FPGA model:

• Spartan3 XC3S5000
• 5M Gates, 74K logic cells, 66K CLB
• 100 MHZ
• 256 Macrocells

Flash Memory:

• 32 Mbits divided in 2 sections
• One section for Safe back-up Configuration
• One section for the User Configuration

FPGA Configuration:

• Using JTAG port
• Using Signal-Wire Serial Link (see below)
• Using PCIe X1 Serial Link

User Connectors:

• 3 x PC104 type (120 positions each) robust connectors
• 296 x DIO  (3.3v) 
• 1 x Master Reset
• 1 x General Purpose Clock

Communication connector:

• 1 x High Speed Communication connector (20 pairs)
• 14 x buffered DIO (3.3v)
• 1 x PCIe X1 End Point (2.5 Gb) using the PCIe Bridge
• 1 x Signal-Wire (Opal-RT proprietary Serial Link, Full-Duplex, 8/10 encoding, 625 Mbit/s) using the Ethernet SERDES
• 1 x RTSI signal for I/O synchronization
• 1 x RESET signal

JTAG  ports:

• 4 x JTAG independent ports (FPGA, CPLD, PCIe Bridge, Ethernet SERDES) 

LED Indicators:

• 13 x LEDS indicators for status and monitoring
• 1 x LED indicator for all DC supplies monitoring

EEPROM:

• 1 x EEPROM (8Kx8) for Identification and confidential data, write-protection by jumper

Other Hardware:

• 1 x RESET Push-Button
• Test-Points

Power Input:

• Main Input: +5 VDC @ 3 Amp on PC104 connector
• On-board generation of dedicated DC supplies (3.3v, 2.5v, 1.8v, 1.5v, 1.2v)

Dimension:

• 3 inches (76 mm) x 6 inches (153 mm)

Software Utilities:

• Flash-Update able to download the FPGA bitstream directly from the application

Software Requirements

• RT-LAB 8.3.x and over 
• Matlab R2007b or R2008a with RTW
• Xilinx ISE 10.1 SP3
• Xilinx System Generator 10.1.03