Reconfigurable FPGA Platform and I/O Interface

High-Density Digital I/O, High-Precision Event Capture and High-Speed PWM Output 32-bit

The OP5110 I/O interface from Opal-RT Technologies allows the incorporation of FPGA technologies, for high-speed, high-density digital I/O in real-time models, in RT-LAB simulation clusters. Based on an ultra-high-density reconfigurable module using Xilinx Virtex-II Pro Platform FPGAs, the OP5110 allows the inclusion of up to 128 channels of Digital I/O, operating at up to 100 MHz cycle frequencies, with a pulse resolution down to 10 ns.

This means that you can capture or generate events between the simulation time steps to an accuracy of 1 µs to incorporate very precise timing into the model for, say, IC engine ignition sparks or IGBT switching in an electronic power converter. An effective precisI/On better than 1 µs can be obtained when combining the FPGA event detection with specialized real-time interpolation algorithms included in the RT-EVENTS block set

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