Reconfigurable FPGA Platform and I/O Interface

High-Density Digital I/O, High-PrecisI/On Event Capture and High-Speed PWM Output External Processor, SignalWire Interface

Programmable Xilinx Virtex II Pro FPGA processor board for external installation Up to 64 software-configurable Digital I/O lines for event capture/generation, PWM I/O and user functions LocatI/Ons for two mezzanine function modules for signal capture/conversion Up to 32 16-bit Analog I/O channels, simultaneous sampling at 1 MS/s per channel (optI/Onal mezzanine modules) SignalWire port for ultra-low-latency data communications Library of drag-and-drop RT-LAB blocks for Simulink

The OP5130 allows the incorporation of FPGA technologies in RT-LAB simulation clusters for distributed execution of HDL functions and high-speed, high-density digital I/O in real-time models. Based on the Xilinx Virtex-II Pro FPGA, the OP5130 can be installed in either a 4U slot in an RT-LAB HILbox or an external signal conditioning chassis for remote signal I/O, communicating with the target PC via the new SignalWire ultra-low-latency real-time networking interface.

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