OP5130 - Description

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• Programmable Xilinx Virtex II Pro FPGA processor board for external installation
• Up to 64 software-configurable Digital I/O lines for event capture/generation, PWM I/O and user functions
• Locations for two mezzanine function modules for signal capture/conversion
• Up to 32 16-bit Analog I/O channels, simultaneous sampling at 1 MS/s per channel (optional mezzanine module)
• SignalWire port for ultra-low-latency data communications
• SCXI Form-factor for 4U HILbox
• Library of drag-and-drop RT-LAB blocks for Simulink

The OP5130 is one of the key building blocks in the modular OP5000 I/O system from Opal-RT Technologies. It allows the incorporation of FPGA technologies in RT-LAB simulation clusters for distributed executI/On of HDL functions and high-speed, high-density digital I/O in real-time models. Based on the Xilinx Virtex-II Pro FPGA, the OP5130 can be installed in either a 4U slot in an RT-LAB HILbox or an external signal conditioning chassis for remote signal I/O, communicating with the target PC via the new SignalWire ultra-low-latency real-time networking interface.

In addition to the FPGA and digital I/O capabilities of the OP5110 and OP5120, the OP5130 includes two interfaces for mezzanine function modules that allow the incorporation of task-specific I/O hardware, such as high-speed analog signal capture and generatI/On.

The SignalWire port on the OP5130 allows you to connect your distributed processors together to operate at faster cycle times than ever before. This real-time link takes advantage of the FPGA power to deliver up to 1.2 Gbits/s full-duplex transfer rates, with a latency of 200 ns - almost twice the rate of IEEE 1394 (FireWire) and more than 10% of the latency - allowing you to run distributed simulatI/Ons at cycle times of less than 10 µs without data overruns.

Through the SignalWire connection to either an OP5110 or an OP5120 on board the RT-LAB target PC, the OP5130 provides an external platform for additional data acquisitI/On and signal conditioning modules. This will allow many I/O channels to be remotely captured and generated via the real-time simulator, thus eliminating electrical noise problems associated with long runs of analog signal cables. The OP5130 can be connected to as many OP5200 passive carriers as needed, and you can daisy-chain several OP5130s. The only limiting factor is the physical space and the bandwidth required by the overall simulation.

Furthermore, FPGA developers can incorporate their own functionality, using their HDL development tools, through the SignalWire interface without the need for connecting to the JTAG interface. Bitstreams can be uploaded and stored on the built-in Flash memory for instant startup.