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Reference Number: AA-01544// Views: AA-01544// Created: 2018-10-15 08:02:53// Last Updated: 2018-10-17 07:03:40 Problem & Solution Glitches on the MMC output voltage when MMC4 or MMC 5 model is simulated on a slave FPGA ProblemWhile MMC4 or MMC5 are simulated on a slave target, the natural rectification results, i.e Vdc, tun out to have abnormal large jitters (about 1%): SolutionThis problem exist with MMC4 and MMC5 blocks. To fix the issue, please go to the block FPGAValve, right click and "disable link" of this block to library and then add a delay to the 3rd output of the s-function as the picture shown. In the near future, an independent MMC library will be created and user can find the correct block there. |