Support : Knowledge base

Knowledge Base

Welcome to OPAL-RT’s Knowledge Base

OPAL-RT offers a repository of support information for optimal use of its technology.

Loading…

Please note that OPAL-RT knowledge base is not fully optimized for mobile platforms.

For optimal experience, use a desktop computer.

Reference Number: AA-01958// Views: AA-01958// Created: 2020-10-05 21:55:03// Last Updated: 2023-04-07 18:18:43
NI Platform Tools
Power Electronics Add-On for VeriStand: Error 8302 with Exit Code -1 when Loading SPS Circuit Model

Problem

When I load my Simscape Power Systems circuit or deploy my project in NI VeriStand, I encounter the following error:


NI VeriStand:  External Interface Framework.lvlib:Command Line Error.vi

The requested executable did not execute successfully and returned exit code -1 and error message :

 __

 __ 

 __ 

Possible error causes:

1.If the executable was compiled from MATLAB the run-time engine installed is missing or doesn't match the one needed.

2.If the executable is a JAVA executable the JAVA run-time engine installed is missing of doesn't match the one needed.

3.The required application parameters are missing or wrong.

4.Dependencies of the application are missing or not mapped correctly.


Solution

To parse a circuit model created in Simscape Power Systems, the Power Electronics Add-On must call MATLAB and the MATLAB Runtime Engine version 9.1.


First, confirm that both the MATLAB Runtime Engine version 9.1 and the JAVA Runtime Engine have been installed on the Host computer, as indicated in the Software Requirements section of the Wiki Help documentation.


If this does not resolve the issue, it is possible that the error is caused by a corrupted MCR cache.  To repair the cache:

1. In the MATLAB command line, enter the command to obtain the file path of the MCR directory.  It is typically located here C:\Users\\AppData\Local\Temp\\mcrCache9.1 

2. Close all instances of MATLAB and VeriStand

3. Navigate to the MCR cache directory and delete the folder mcrCache9.1

4. Relaunch VeriStand and attempt to load the circuit model