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Reference Number: AA-02032// Views: AA-02032// Created: 2021-09-02 20:02:25// Last Updated: 2021-09-02 20:16:12 Problem & Solution RT-XSG - Generation status - Error Exit status '9' - MuSE Remote ProblemWhen generating a firmware (bitstream) using the MuSE Remote option (RT-XSG v.3.2.1+), the following error is obtained: Generation Status: The exit status of the RT-XSG generation process is '9'. Look (...) In the Vivado Report File folder: XSG_FPGAModelGeneration.log ERROR: [Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: (...) SolutionThe issue is present for Xilinx Vivado 2018.1 and 2018.2 versions. Please use a different version. If that is not possible, please contact our Support Team mentioning this KB article in the description. |