Flying capacitor converter simulation for multilevel designs

Key Takeaways

• A flying capacitor converter earns its efficiency and density only while every capacitor holds its target voltage, and the switching pattern is the sole thing keeping it there.
• Natural balancing is slow and weakens at light load, during bus steps and at start-up, so active balancing has to be designed and proven alongside the current loop.
• Averaged models hide capacitor drift, which makes a switching-accurate model run in real time against the controller the practical way to validate multilevel control.

A flying capacitor converter only delivers its efficiency and density gains when every capacitor holds its share of the bus voltage, and proving that takes a model that reproduces each switching event.

The appeal of the topology is easy to measure. A 10-level flying capacitor module built at the University of California, Berkeley reached 38.4 kW/kg at 98.95% peak efficiency. Those gains come from splitting the bus voltage across many low-voltage switches, which shrinks the filter.

The catch is that nothing holds those capacitor voltages in place except the switching pattern itself. Balance drifts when timing, load or bus voltage moves, which makes it the part of the design you can’t afford to approximate. A switching-accurate model, run offline and then through real-time simulation against the actual controller, is how you test multilevel control against the conditions that upset it.

What a flying capacitor converter does inside a multilevel stage

A flying capacitor converter is a multilevel topology that builds intermediate voltage levels from capacitors that float between series-connected switch pairs. Each capacitor holds a fixed fraction of the bus voltage, so every switch blocks only one step of it. The output filter sees smaller voltage steps at a higher effective frequency.

A generic 5-level leg on an 800 V bus uses 4 complementary switch pairs and 3 flying capacitors charged to 200 V, 400 V and 600 V. Each switch blocks 200 V. With phase-shifted carriers at 100 kHz per pair, the inductor sees ripple at 400 kHz.

That arithmetic explains why solar inverters, aircraft drives and data centre power stages use the topology. Every voltage level exists only while the capacitors stay at their targets, and no clamping network enforces that.

How flying capacitor voltage balancing works through switching

Flying capacitor voltage balancing works because the load current passes through each capacitor in both directions during a switching period. One switch state charges a capacitor and a matching state discharges it. When every switch pair runs the same duty cycle with evenly shifted carriers, the two charges cancel and the voltage holds.

A 3-level leg shows the mechanism cleanly. Two switch states both place half the bus voltage on the output. One routes the inductor current into the single flying capacitor and the other draws the same current back out. Phase-shifted modulation visits both states for equal time, so the capacitor settles at half the bus without any sensor. Engineers call this natural balancing. Its restoring force comes from ripple current and circuit losses acting on any imbalance, so it’s slow and it scales with how much ripple the operating point produces.

Why natural balancing fails under practical operating conditions

Natural balancing fails when the charge delivered to a capacitor stops matching the charge removed, or when the restoring ripple current becomes too small to correct an error. Gate timing mismatch, light load, bus voltage steps and start-up all create one of those conditions, and each shifts voltage onto switches that weren’t rated for it.

Consider a duty mismatch of 1% between two switch pairs caused by unequal gate driver delays. At 100 kHz that’s a 100 ns error. It pumps a small net charge into one capacitor every cycle, and the voltage walks away from its target until circuit losses arrest it. 

“Nothing looks wrong at the output until a switch exceeds its rating.”

Bus transients are harsher. If the 800 V bus feeding a 5-level leg steps up by 100 V, the capacitor targets move to 225 V, 450 V and 675 V, but the capacitors respond at the slow natural balancing rate. Until they catch up, the switch pair nearest the bus carries most of the extra voltage.

Each condition asks something specific of the model.

How to control a flying capacitor converter with active balancing

You control a flying capacitor converter with two loops that share the same switches. An outer loop regulates output current or voltage through the average duty cycle. A balancing loop then trims the duty or the choice of redundant switch state for each pair, so every capacitor returns to its target.

The balancing loop needs to know the capacitor voltages. A 6-level leg carries 4 flying capacitors, each floating at a different potential, and an isolated sensor on every one adds cost and delay. Many designs estimate the voltages instead, which makes balancing quality depend on sampling instants and estimator tuning.

The two loops also interact. A balancing correction disturbs the output current, and a fast current loop will fight it. You’ll set the balancing bandwidth below the current loop and then need proof that it still recovers from a bus step in time. A three-phase 1.5 kV, 15 kW solar inverter built on this topology at the University of Illinois reported total harmonic distortion of less than 0.25%, and the same research listed active balancing and start-up among its main contributions.

What a flying capacitor multilevel simulation must resolve

A flying capacitor multilevel simulation must resolve every switching event of every switch pair, because capacitor balance is decided by the timing differences between them. An averaged model replaces the switches with duty-controlled sources and assumes the capacitors sit at their targets. It will predict the output well and report nothing about balance.

Timing resolution is the first requirement. A 100 kHz carrier has a switching period of 10 µs, and the mismatch that causes drift is around 100 ns. A fixed-step solver that only registers gate edges on a 1 µs grid rounds that mismatch away or invents one. The model has to place each edge between steps, or step finely enough that rounding doesn’t matter.

Device and parasitic detail comes second. Dead time, the direction of inductor current at each commutation and capacitor series resistance all alter how much charge moves per cycle. 

“Leave them out and the model balances better than the hardware will.”

Run length is the third pressure. Balancing dynamics unfold over thousands of switching cycles, and each cycle needs fine resolution. Offline start-up studies get slow enough that engineers start skipping cases.

Building a real-time model of a flying capacitor converter

A real-time model of a flying capacitor converter runs the switching-level circuit on an FPGA, so each capacitor voltage is computed within a time step far shorter than the switching period. Your production controller connects through its own gate and sensor signals.

This is hardware-in-the-loop testing applied to the one behaviour averaged models can’t show. OPAL-RT simulators execute power electronics circuits on FPGA-based solvers such as eHS, which is how the gate timing your controller produces reaches the simulated capacitors. With the controller in the loop, you can run cases that are risky on a prototype and repeat them after every firmware revision. These 5 cover most of what upsets balance.

• Start-up with every flying capacitor discharged and the precharge sequence active
• Bus voltage steps and sags at full and light load
• Load dumps that reverse the inductor current
• Deliberate gate delay mismatch on a single switch pair
• Loss of one capacitor voltage measurement during operation

What to validate before trusting a flying capacitor design

Validate balance under disturbance before you trust any efficiency or density figure. A flying capacitor design is sound when every capacitor returns to its target after start-up, a bus step, a load dump and a timing fault, and when every switch stays inside its voltage rating while that recovery happens.

Teams that get this wrong usually tune the current loop on an averaged model, confirm steady-state waveforms on a prototype and meet the balancing problem when a device fails during a transient nobody simulated. Putting balancing first reverses that order. You start with the switching model, write the disturbance cases down as pass and fail criteria and rerun them whenever the control code is revised.

OPAL-RT captures flying capacitor voltage balancing in real time, so your multilevel control is validated against the same dynamics that destabilize it before any silicon is at risk. The converter’s self-balancing is fragile, and that’s acceptable. Fragile behaviour you’ve measured across every operating point is something you can design around.