How to model and control a T-type three level inverter

Key Takeaways

• A T-type leg reaches three voltage levels with four devices per phase, trading uniform device stress for a shorter conduction path.
• Neutral point drift sets the practical control limit, and redundant switching states inside the modulator are where it gets corrected.
• Device level modelling of the midpoint branch is what makes three-level control results in the lab hold up on hardware.

A T-type inverter leg reaches three output voltage levels with four switches per phase, and its bidirectional midpoint path carries most of the control difficulty.

The topology adds a bidirectional switch between the phase output and the midpoint of a split DC link. That branch gives a clean zero state without the clamping diodes an NPC leg needs, and fewer devices in the path means lower conduction loss. What you give up is uniform device stress across the leg.

Grid-side converters test that tradeoff hardest. Solar plants make up 51% of the 86 GW of new utility-scale capacity United States developers plan to bring online in 2026, and nearly all of it leaves through a voltage source inverter. Making the neutral point behave under unbalanced load is what separates a working design from a model that only looks right.

How a T-type leg produces three voltage levels

A T-type leg produces positive, zero and negative output levels from four switches. The outer pair connects the phase to the upper or lower DC rail. The bidirectional midpoint switch ties the phase to the capacitor junction, so the output steps in half-rail increments.

Take an 800 V link split into two 400 V halves by series capacitors. The outer switches swing the phase between plus and minus 400 V around that junction, and the midpoint branch holds it at zero. The line to line waveform then carries five levels.

That halving pays for the extra devices. Filter inductors shrink, common mode content drops, and the dv/dt reaching motor windings falls with it. You’ll also find the harmonic spectrum moves higher, since the effective output switching frequency doubles.

Why the bidirectional midpoint switch complicates commutation

The midpoint branch has to block and conduct in both directions, so it’s built from two devices back to back. Every transition between the zero level and a rail level commutates between that pair and one outer switch, and current direction decides which device turns off.

Common builds put two IGBTs in a common emitter arrangement, or two reverse blocking IGBTs face to face. A silicon carbide design often uses two MOSFETs source to source. Each option changes gate drive count, isolation and reverse recovery, so treating the branch as one ideal switch misses the loss split.

Dead time is the second complication. Commutation to a rail passes through a window where neither device conducts, and current freewheels through a diode you didn’t plan to use. Those small voltage errors accumulate as low order distortion. Solve cross-conduction protection in a model before the bench.

The main difference between T-type and NPC inverter legs

The main difference between a T-type and a neutral point clamped leg is where the blocking voltage sits. An NPC leg splits full rail voltage across two series devices and clamps the junction with diodes. A T-type leg keeps two full voltage outer switches and routes the zero state through a lower voltage branch.

Count the conduction path and the difference gets concrete. At the zero level an NPC leg carries current through two series switches plus a clamping diode, while a T-type leg uses the two devices of the midpoint branch. At a rail level the T-type leg uses one device.

The crossover point matters more than any single loss figure. NPC pulls ahead past roughly 1 kV, where T-type outer devices need blocking capability that gets expensive. Below that, the T-type leg usually wins on total loss.

How voltage stress splits across T-type devices

Stress splits unevenly by design. The two outer switches block the full link voltage and take the hard switching transitions, while the midpoint pair blocks half the link under much softer conditions. Thermal design has to follow that asymmetry.

A 650 V rated midpoint pair under a 1200 V rated outer pair is a normal bill of materials for an 800 V link. The outer devices absorb the switching loss of every rail transition, so their junction temperature climbs with frequency. The midpoint devices conduct longer, so on-state resistance matters more there.

Two consequences follow. Heatsink layout stops being symmetric, because the hottest die isn’t in the middle of the module. Derating curves become topology specific, since higher switching frequency punishes the outer devices while higher current punishes the branch. One lumped loss figure will size cooling wrong.

“Heatsink layout stops being symmetric, because the hottest die isn’t in the middle of the module.”

What causes neutral point voltage drift in T-type inverters

Neutral point drift comes from unequal charge moving into and out of the DC link junction. Each time a leg sits in the zero state, phase current flows into or out of the capacitor midpoint. Those contributions rarely cancel over a fundamental cycle, so one capacitor charges while the other discharges.

Run a three-phase T-type inverter at unity power factor and the midpoint current averages near zero. Push power factor down or inject reactive current for grid support and the average stops cancelling. Capacitor voltages walk apart until output levels lose symmetry.

Correction usually happens inside the modulator. Redundant switching states give two ways to synthesize the same output vector with opposite effects on the junction, so a balancing term picks the state that pushes the capacitor voltages back toward each other. Larger link capacitors slow the drift and buy time. Get that balance wrong and you’ll see ripple you can’t control.

Choosing a modulation scheme for a T-type inverter

Modulation sets switching loss, harmonic content and how much authority you keep over the neutral point. Level shifted carrier PWM is simple and gives predictable spectra. Space vector modulation exposes the redundant states directly, which makes junction balancing straightforward at the cost of computation.

Five factors usually settle the choice.

• Switching loss budget, since discontinuous schemes clamp each phase for 120 degrees.
• Neutral point authority, which depends on how much redundant state selection a scheme leaves available.
• Harmonic performance near the filter corner frequency, measured against your grid code.
• Common mode voltage, which matters for motor bearing currents and transformerless solar builds.
• Controller execution time, because predictive schemes evaluate every candidate state each sampling instant.

Model predictive control has become popular on T-type legs because one cost function weighs current tracking and capacitor balance at once. Each state gets judged on its actual effect rather than an averaged model. The tradeoff is a variable switching frequency and a load heavy enough to need an FPGA.

Simulating T-type midpoint behaviour in real time

Real-time simulation of a T-type leg has to resolve the midpoint branch as two separate devices with their own conduction states. Averaged models hide the commutation detail balancing control acts on, so behaviour validated against an averaged plant won’t match hardware.

Efficiency margins make the case for that fidelity. A 2.2 kW silicon carbide T-type prototype measured 99.29% efficiency at 20 kHz against 98.43% for a two-level baseline, with distortion falling from 3.11% to 1.36%. Margins that thin only appear if the model accounts for loss device by device. OPAL-RT solves the T-type leg on FPGA at sub-microsecond time steps, so a controller under test meets the commutation sequence it will see on hardware.

Hardware in the loop testing is where the payoff lands. You can drive the production controller with a plant model carrying capacitor tolerance, dead time and unbalanced grid conditions, then watch the balancing loop respond at full rate. Fault cases that are expensive on a bench run safely in the model.

“Margins that thin only appear if the model accounts for loss device by device.”

Where T-type control discipline shows up in the lab

T-type designs succeed or fail on the details of the midpoint branch. Device selection, dead time, capacitor sizing and the balancing term all act on the same node, and none of them can be tuned in isolation. Teams that treat them as one problem finish sooner.

The pattern repeats across projects. A team that validates its balancing loop against an averaged plant passes in simulation, then chases low order harmonics on the bench for weeks, because the model never produced the charge imbalance hardware produces. A team that resolves the branch finds that problem in a week.

Careful modelling of the midpoint path is what makes three-level control schemes testable against the topology as it’s actually drawn, and it’s why OPAL-RT builds the T-type leg at device level rather than as an averaged block. That discipline doesn’t make design work easier. It makes your lab results mean something.