Validating GaN and SiC converter designs in real time

Key Takeaways

• Wide-bandgap converter validation starts with time resolution because unresolved switching events make later control, thermal, and protection results less reliable.
• GaN and SiC designs need validation flows that keep topology, parasitics, and timing intact across simulation, bench correlation, and HIL.
• The strongest teams set timestep first, then expand model scope only after switching behaviour, loss correlation, and protection timing hold up.

Validating a GaN converter or SiC converter in real time starts with one non-negotiable rule: your simulator must resolve the switching events that define the hardware you plan to build.

Wide-bandgap power stages now sit inside products that ship in large numbers, so hidden switching errors carry a direct cost in rework, bench time, and missed design targets. Global electric car sales exceeded 17 million in 2024, and those platforms rely on converters whose timing margins sit in nanoseconds. A model that smooths sharp events will look stable long before the hardware is safe. You need a validation flow that keeps switching physics visible from the first model to HIL test.

Converter validation starts with switching events you can resolve

Converter validation starts when your model resolves the switching events that set current, voltage, and loss. If the timestep skips those edges, every later result rests on blurred physics. That applies to a GaN converter and a SiC converter alike. You must see the event before you can trust the response.

Consider a 650 V half bridge with 15 ns rise time and 8 ns dead time. A 250 ns simulation step will still produce neat waveforms, yet it will miss the overlap that sets switching loss and the ringing that sets device stress. Lab teams then wonder why the controller looked clean in simulation but trips on the first hardware pulse. The issue usually starts where the model stopped resolving the edge.

You’re validating more than average current and voltage. You’re validating the exact order of turn-on, turn-off, diode recovery, and loop energy exchange. That is where false confidence begins if the solver is too slow. 

“Wide bandgap validation works best when you treat switching resolution as the first acceptance gate.”

GaN converter simulation often needs timesteps below 100 ns

GaN converter simulation often needs timesteps below 100 ns because the important behaviour sits inside very short edges, dead times, and controller events. A usable step size comes from the fastest electrical transition you must preserve. Coarse steps can still show power flow correctly. They won’t show the timing error that breaks the design.

A totem pole power factor correction stage makes the point clearly. If the high-frequency leg commutates in tens of nanoseconds, a 50 ns step can capture turn transitions and dead time interaction, while a 200 ns step smears them into one averaged event. Gate delay mismatch then disappears from the simulation even though it still exists in hardware. You’re left tuning around a model that hides the fault path.

Published material data place GaN critical electric field near 3.3 MV/cm, compared with about 0.3 MV/cm for silicon. That helps explain why GaN edges expose coarse-step error so quickly. You should start from measured or expected switching speed. Then set the timestep small enough that dead time, overlap current, and dv/dt-related effects stay visible.

SiC converter tests must expose commutation loop parasitics

SiC converter tests must expose commutation loop parasitics because overshoot, ringing, and false turn-on are set by layout as much as device data. A clean schematic is not enough. Loop inductance, device capacitance, and gate return paths shape the event. Those details decide if your SiC converter survives the transition you just commanded.

A traction inverter phase leg shows this quickly. The same SiC MOSFET pair can look calm with an ideal DC link and then overshoot badly when you add the actual busbar loop and gate loop inductance from the mechanical design. Lab leads can make the first prototype look worse than the production layout. You need the simulation to expose both cases before the bench does.

Parasitics also affect the controller side. Current measurement timing and fault thresholds often get tuned against waveforms that already include ringing. If the model removes that ringing, your thresholds will be set for a converter that doesn’t exist. Validation is stronger when commutation parasitics are treated as part of the design.

SiC MOSFET testing should verify switching energy curves

SiC MOSFET testing should verify switching energy curves across current, voltage, temperature, and gate resistance because those curves anchor your loss model to physical behaviour. A single nominal point is not enough. Your converter operates across a range. Validation must check the range you expect to ship.

A double pulse test is still one of the clearest ways to do this. You can sweep current, bus voltage, and gate resistor values, then compare measured turn on and turn off energy with the model used in the full converter simulation. A mismatch at high current often points to missing parasitics or incorrect capacitance assumptions. That matters because optimistic energy values will understate junction temperature and margin.

The useful question is not just whether the waveform looks right. You also need to ask if switching energy trends move correctly as operating conditions shift. A model that tracks shape but misses slope will still mislead you on efficiency, cooling, and protection. Testing a SiC MOSFET converter needs correlation between pulse-level measurements and full-stage behaviour.

Real-time solvers should run the design as built

Real-time solvers should run the design as built because validation loses value once you start simplifying the converter to fit the simulator. A solver that forces averaged switches or stripped parasitics changes the behaviour you are trying to verify. That gap shows up later as rework. It starts when the model stops matching the intended hardware.

Take an interleaved bidirectional converter with active clamp paths, measured stray inductance, and tight dead time constraints. If the platform can’t execute that topology directly, teams often replace detailed switches with averaged elements or remove commutation paths just to meet execution limits. The simulation still runs, yet the validation target has shifted. That is the problem high-speed power stage solvers were built to avoid.

OPAL-RT’s High Speed Converter Solver shows why execution speed matters because it runs advanced GaN and SiC topologies at timesteps down to 36 ns. That matters as a modelling discipline more than a feature line. You keep the gate timing, parasitics, and switching structure that belong to the design. Your HIL results then reflect the converter you plan to power up.

HIL testing validates control timing before hardware faults appear

HIL testing validates control timing before hardware faults appear because the controller reacts to sampled signals, pulse updates, and delay chains, not to idealized power stage equations. You need those time relationships closed in the loop. That is where subtle errors surface early. It is also where expensive bench surprises can still be avoided.

Current sampling near a switching edge is a common case. If the ADC sample lands during ringing, the estimator and protection logic can make a bad decision even though average current is correct. HIL lets you test alternate sampling offsets, digital filters, and blanking windows without risking hardware. You can watch how a controller behaves when timing looks acceptable on paper but awkward in practice.

This matters for wide-bandgap converters because control margins are often tighter than teams expect. Dead time compensation, synchronous rectification timing, and current reconstruction all depend on edge placement. A controller that looks solid with averaged plant models can become noisy once switching detail is restored. HIL earns its place when it exposes those timing interactions before the first power stage fault.

Protection logic needs nanosecond-accurate fault reproduction

Protection logic needs nanosecond-accurate fault reproduction because wide-bandgap faults unfold on the same time scale as the switching events that trigger them. If the model stretches or smooths the fault, the trip path is validated against the wrong event. That creates false comfort. Protection only counts when the reproduced fault is physically plausible.

Short circuit turn-on is a good example. The important question is not only if the controller declares a fault, but how fast current climbs, when desaturation logic reacts, and what voltage stress appears during turn-off. A model that injects fault current as a slow ramp will make the trip look orderly even if the actual converter would see a violent peak. You need the same rigour for false turn-on and gate skew cases.

Protection timing also interacts with sensing hardware and firmware structure. Comparator delays, digital filtering, and reset logic can all appear harmless until the event is compressed into its true duration. Once that timing is visible, nuisance trips and late trips stop looking random. They become validation findings you can fix with confidence before high-energy testing starts.

Validation plans should rank timestep before model scope

Validation plans should rank timestep before model scope because timestep decides which physical events remain visible. A broad model running too slowly will still hide the evidence you need for acceptance. A narrower model with the right time resolution will answer the important question first. That order will save you time and false starts.

The planning sequence is straightforward when you treat switching fidelity as the first filter. Start from the measured or expected edge speed, then lock the simulation step that preserves it. Add only the model detail needed to explain the behaviour you are testing. Expand the scope after the event-level physics hold up.

• Set the timestep from the fastest edge and shortest dead time.
• Keep the physical topology intact before adding extra system detail.
• Include measured parasitics where overshoot or ringing affects acceptance.
• Correlate switching energy with bench data before trusting thermal results.
• Use HIL to test control and protection timing against the resolved plant.

That sequence works because it mirrors how wide-bandgap hardware fails. Teams that follow it spend less effort defending optimistic models and more effort fixing the few parameters that move risk. OPAL-RT fits naturally into that workflow when the target requires nanosecond-class execution without rewriting the converter into a simpler form.

“Good validation is about making the hard parts visible early enough to act on them.”