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  • Technical Paper
  • Power Systems
  • Hardware-In-the-Loop (HIL)

A Hardware-in-the-Loop SCADA Testbed

Author : Hossein Ghassempour Aghamolki, Zhixin Miao, Lingling Fan
Conference : North American Power Symposium (NAPS), 2015

USF Smart Grid Power System Lab (SPS) has developed a hardware-in-loop (HIL) SCADA testbed. This paper describes several communication and control architectures of the testbed with different hardware and software combinations. This testbed will be used to test energy management schemes, power grid cyber attack and mitigation strategies. Phasor Measurement Units (PMUs) synchronized with the common GPS reference signal are used to capture data from a real smart grid system as well as a simulated power network in OPAL-RT’s real-time simulator. Captured data will be sent to OSIsoft’s PI-Server database via different protocols.