This work aims to present a solution to expand the capability of OPAL-RT Simulators for modeling high demanding power system components, like Frequency Dependent Network Equivalents (FDNE).
Due to its complex nature, this component can demand several processing cores for its individual solution keeping the required time-step, when normally executed on multi-core CPUs based hardware.
The development of a multi-port FDNE component, modeled using FPGAs hardware, can save precious Simulator computational resources while at the same time improving the precision of the simulation.
2. Scope of the Work
The mathematical models based upon rational functions approximation are well established on technical literature for a precise representation of FDNE. Such kind of components are generally used when the modeling of the intended power network does not fit in the available simulation hardware.
The parallel nature of FPGA hardware is very well suited for high-performance multiport FDNE applications, as opposed to the traditional CPU hardware.
The mentioned multiport FDNE model is automatically generated with any numbers of poles and ports and it is also supported by a passivity-enforcement post-processing correction. Additionally, a method that shifts the frequency axis of the Vector Fitting input frequency responses is proposed to correct the warping error introduced by the trapezoidal integration method. These enhancements allow for numerical stability of the model and the perfect match between the original network frequency response and that one obtained by the FDNE after the integration with the time-domain simulation.
In order to achieve a more general solution for the FDNE model implementation on FPGA hardware, the Xilinx Vivado Suite was chosen. As a result, a co-simulation interface between OPAL-RT and RTDS simulators could be stablished to take advantage of the hardware resources available in the simulation lab.
The comparison of results has showed that the developed model worked as intended. This FDNE model can be executed on FPGA hardware with sufficiently small time-steps, suitable for real-time operation, much lower than the typical fifty microseconds used for large systems EMT simulation.
This type of application represents an efficient solution to increase the representation capacity in the short term when there are budget limitations that delay expansion through the acquisition of a larger number of simulator’s chassis or core licenses.