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Reference Number: AA-00731// Views: AA-00731// Created: 2011-03-28 05:00:00// Last Updated: 2016-06-27 14:48:41
Problem & Solution
Analog Output (DAC) Reset to 0V

Problem

1.My analog outputs (DACs) are still outputting the last signal waveform when I reset the model. Is it possible to have them set back to 0VDC at reset?

2.My analog outputs (DACs) are holding the last DC value of the signal waveform when I reset the model. Is it possible to have them set back to 0V at reset?

Solution

Yes it is possible, the 2 questions are related to two different issues.

1.To solve this problem, you need a new DAC mezzanine. Older revisions of DAC mezzanine must be modified in order to allow a DC reset instead of keeping the waveform as the output. Revisions 1.6 and under are concerned by this problem. Revisions 2.0 and up are known to solve the problem. You may fill an RMA request in order to get your mezzanines replaced.

2.To solve this problem, the bitstream file you are using must be modified. If you directly connect the DataIn block, using your own concatenation/deconcatenation, to the analog output block, you may observe the described behavior. In order to fix this, you must absolutely use the AOut Unpacking module, found under RT-XSG / Your FPGA platform (either ML605 or OP5142) / Data Packing and Unpacking library. If you possess RT-XSG, you can easily implement that in your FPGA model. Note that it is recommended to build the bitstream with the latest RT-XSG version available at the moment. We recommend to use RT-XSG 2.1b5 or higher. If you are not a RT-XSG user, please contact support to get a new bitstream file (please attach your current bitstream file).