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Reference Number: AA-00871// Views: AA-00871// Created: 2013-08-05 05:00:00// Last Updated: 2015-05-07 14:09:55
General Article
The .bin (bitstream) file and .conf (configuration) file explained

The .bin (bitstream) file and .conf (configuration) file explained

If your project includes an OP5142 or a ML605 FPGA card, you might have received a .bin and a .conf file along with the integration model of your target computer. Therefore, you may be wondering what is the exact purpose of these two files. The current Knowledge Base article has the purpose to introduce you to the use of these files.

Correlation with the hardware

The bitstream is a VHDL coded file that is meant to be loaded in the FPGA card of the target computer to configure it prior to the execution of the real-time simulation. Its purpose is to configure the FPGA card according to the IO card assembled on the target computer. It specifies the FPGA card where to expect inputs, where to send outputs and what operations to be done on the signals in between. It also specifies what is the type of those IOs. For instance, a digital IO card can be configured to work with Pulse-Width Modulated signals (PWMIO), Time-Sampled signals (TSDIO), Static signals (SDIO) or Quad Encoder signals (QEIO). The analog IO card, on the other hand, can be configured to work with classic analog signals (AIO) or modulated analog signals called resolver signals (RIO). This means that for a same hardware configuration, you may need more than one bitstream if your requirements change. Finally, note that the signal type is defined by sets of 8 channels meaning that one digital card can work with four different signal types and an analog card can work with the to analog signal types during the simulation.

Correlation with the software

The configuration file is a .txt file that is used to specify to the RT-LAB model what is the IO configuration available on the system. Thus, it has only the purpose of linking the FPGA bitstream to the model. All errors you receive about the IOs on the RT-LAB model are caused by the configuration files who verifies that you inputted the proper block functions (signal type) and Data port number (hardware location) for all the IO used in the model. Also note that your problem is not so easily solved has by modifying the .conf file to "your needs" it would only cause the error to not be detected and appear later. The .conf file is often used to figure out the configuration of the bitstream file since the last is not readable (content protected). A more advanced user may work only with the "DataIn Send" and "DataOut Receive" blocks. In such a case, no .conf is necessary for the model to run.

Changing the .bin and the .conf

The .bin and the .conf files are not easily changed. The bitstream is a configuration file compiled by the Xilinx Design Tools software and the OPAL-RT's RT-XSG libraries. It is developed using a block diagram structure similar to simulink while configuring low-level operation on binary structured signals. The model developed using the block diagram always needs to be compiled in order to be converted into a VHDL coded file. These two operations are very long and time consuming for our developers, meaning that most of our clients only receive one .bin file with their system that is meant to answer all their real-time simulation needs. This said, it is possible to request a new bitstream configuration, but such a request will only be accepted if necessary for the ongoing project and not for the purpose of only testing the other possibilities of RT-LAB. We offer a variety of default bitstream for these kind of tests that, even though they would not respect the entire client configuration, would permit to test the function wanted.

Reading the .conf file

Using the picture of a configuration file below this paragraph, we will make an example on how to read the configuration file for an OP5600 system. First, by looking at the slot and section, we can see that the current bitstream is done for a hardware configuration with an analog out card in group 1A, an analog in card in group 1B, a digital input card in group 2A and a digital output card in group 2B. We have determined that by using the second, third and fourth column. Then, using the first and the fifth columns, we can associate each group of 8 channels with a DataIn port number (for outputs) or a DataOut port number (for inputs). Therefore, we see that, if we specify the DataIn port number 2 in an analog out block in the RT-LAB model, we will be controlling channels 8 to 15 of the analog output card in group 1A. Furthermore, if we specify the DataOut port number 10 in an Event Generator block (TSDO) on the RT-LAB model, we would be controlling channels 8 to 15 of the digital output card. Also, note that even though we could have configured all 32 channels of the digital cards, we only configured 3 subsections meaning that channels 25 to 32 are not used for both digital cards. Then, you will see that DataOut 7 and 8 are declared to be unused. This is to illustrate that the developer has two choices when not using a Data port number, he can either write nothing in the .conf file or declare the line as unused. In addition, LoadIn are only used when the digital cards have QEIO. They have the purpose to initialize the value of these particular channels. Finally, columns representing Count and Size are only to be used by developers and have no use for the actual user.

Location of the .bin and .conf files

The .bin and the .conf files are always to be found in the same directory as the project model. You can have more than one .bin and .conf file in this specific directory, but always make sure that the right .bin file is called by your model if you do so.