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Reference Number: AA-01581// Views: AA-01581// Created: 2019-02-13 01:56:28// Last Updated: 2019-02-18 03:27:36
HowTo
How to record and virtualize simulation results by using RT-XSG scope

With a firmware supporting the RT-XSG scope, it is possible to use RT-XSG Scope to record data from eFPGAsim through using the same resolution of the solver of FPGA (the sampling rate of the eHS or FPGA-based motor solver). It should be noted that the RT-XSG scope only returns one sample per signal at each CPU simulation time step, so it takes the same number of CPU model steps as the Number of samples to transfer a whole buffer of data.Therefore, the time frame (the vector of the time) needs to be reconstructed to represent the actual resolution. One of the approaches is to create the time series by integrating the ratio between the time step of the RT-XSG scope (sampling rate) and the time step of RT-LAB (CPU) model.


The attached example shows how to use RT-XSG scope with the standard firmware for the eHSx128 and motor (on a Virtex-7 platform). The firmware (VC707_2-EX-0001-3_1_8_105-eHSx128gen3s_withMotorsAndIOs-50-05.bin) used in this example can be found at C:\OPAL-RT\eFPGAsim\v1.5.4.41\Common\fpgalib\firmwares.

1. Add a into the console. In the model, it is necessary to put one control panel for RT-XSG Scope, where we could set which signal we want to record in .mat file, specify the sampling rate, and choose which signal to be used for triggering data recording. As for the number of serial input, we put it to one in default.


2. Add a into the computational subsystem. The port of Scope Ch returns the data from eight channels set in the control panel. The unused channel remains zero when less than eight channels are used. The output of Valid will be high when values are being sent from the FPGA. And the port of SOF rises to high when a new frame starts. Therefore those two ports could be used for triggering OpWriteFile module.


RTXSG_scope.zip 73 Kb 73 Kb