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Reference Number: AA-02061 // Views: 124 // Created: 2022-01-20 04:27:34 // Last Updated: 2022-01-21 08:21:47
How to configure the "AOMR-V2" control panel block for customized applications?

How to configure the "AOMR-V2" control panel block for customized applications?

For bitstream that generated with new "AOMR-V2" block by RT-XSG, the relating "Analog Output Mapping and Rescaling V2 block Control Panel" block must be used in SC console to configure the "Analog Output Mapping & Rescaling Controller" block in SM or SS subsystem.

The advantages of "AOMR-V2" compares to "AOMR-V1":

1- Better stability.

2- Better usability: "AOMR-V2" offers more inputs on the block, which making it easier to map many things, especially when you have more than 1 eHS used in your model.

For general application of "AOMR" block, please refer to this KB: How to send Analog Out Signal using the AOMR block? This article only focus on the configurations of "AOMR-V2" control panel block in SC console, as the applications of "AOMR" controller block remains not changed.

Control Panel Block in Library



AOMR Version - This parameter allows to choose between the two available versions of the AOMR block. The V1 allows to configure 1 or 2 lanes: lane 1 is parallel and lane 2 is serial. The V2 version allows to configure from 1 to 8 serial lanes.

Number of lanes - This parameter allows to choose how many lanes to configure. If 0 is selected, only CPU inputs are available.

Open Mapping Table - This button opens the Mapping Table view where the signals assignation, gain, offset, min and max can be tuned.



The number of lanes sections displayed depends on the number of lanes parameter selected in the General box. The CPU inputs section is always available even if 0 lanes are selected.

A lane section constraints:

Source - Scroll down to choose between Custom List and Unassigned. This choice enables the Signals List.

Signals List - Allows to enter the signals list going to the lane. This list must be exhaustive, and the order of the names must match the actual order of the signals in the wire.

The relationship between the number of Lane and AOMR outputs for eFPGAsim demo bitstream are listed in the table below. Note the relationship maybe different if the bitstream is customized.

AOMR Mapping Table

Signal - This parameter sets the signal to be sent to the corresponding Analog Out.

Gain - This parameter sets the gain to be applied on the selected signal.

Offset - This parameter sets the offset to be applied on the selected signal.

Min (Volts) - This parameter sets the AO channel output minimum voltage.

Max (Volts) - This parameter sets the AO channel output maximum voltage.

The formula applied to the output signal is - Output AO voltage = saturate (signal * gain + offset, min, max).


Only CPU Inputs

Set the <Number of lanes> to "zero". Then map each "UserAnalogOut" ports to specific AO channels of AO cards.

With eHS Outputs

Set the <Number of lanes> to "1" or more. A new lane "Lane 1" will show up with 16 eHS outputs configured as default.

Note: User could modify the section of <Signals List> directly when more eHS outputs are required to be observed by "AOMR-V2". Make sure the new added variables have the same format as default and do not exceed the dimensions of licensed eHS.

For example, if 1 eHSx128 is used in the model, the <Signals List> could be added by any variables from 'ehs1.Y1' to 'ehs1.Y128'. Also, if there is not only 1 eHS used in the model with this bitstream, the variables of 'ehs2.Yxx' could be added to observe the second eHS outputs.

After the modifications of <Signals List>, click "Apply". Then, user could map the desired eHS outputs to specific AO channels:


With FPGA-based Motor Outputs

User should first check the type of motors that included in the bitstream. Then add the desired variables to the <Signals List>. Note: the number of lanes maybe increased to 2 or more for configurations.

The observables of each motor blocks that could be added into the <Signals List> of "AOMR-V2" are listed in the following:


1- Dual PMSM-SH Model:


2- Dual PMSM-VDQ Model:


3- Quad Generic Machine Model:

 For example, if user want to observe the resolver signals of machine 1 in "Quad Generic Machine Model", the variables {'sin_res_0', 'cos_res_0', 'Carrier_0'} should be added into the <Signals List> of Lane 2 as the figure below:

For more information about how to generate or upgrade a bitstream with "AOMR-V2", please contact OPAL-RT support: OPAL-RT Technical Support