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Reference Number: AA-01770// Views: AA-01770// Created: 2019-11-22 15:57:16// Last Updated: 2019-11-25 21:43:14
HowTo
OP5607 MUSE Remote SAFE Flash Programming Procedure

Overview

This article assumes that the Xilinx Virtex 7 FPGA, onboard an OPAL-RT OP5607 expansion chassis, has already been programmed with the  *.bit SAFE bitstream as in this KB article. At this point, the FPGA flash can and must be programmed  with the *.bin SAFE bitstream via the SFP fiber optic cable connected to a Central target simulator. 


Procedure

1) Make sure the OP5607 is connected to the Central target simulator via SFP. Usually, unless otherwise specified by OPAL-RT during the delivery of the bitstream, any SFP port can be used.

2) Ideally, use MobaXterm and connect to the Central target simulator. Verify that the SAFE is well programmed on the remote by looking if it is detected by the Central target simulator. To do so, simply run the command below:

/usr/opalrt/common/bin/flash_update -bim

Both the Central and the Remote FPGAs should be detected.


3) At this point, it is confirmed that the SAFE has been properly programmed via JTAG (*.bit file). Now, re-program the SAFE again but via the flash_update command (*.bin file). To do so, use MobaXterm and:

a. Copy the SAFE *.bin file (attached) in the target /home/ntuser/ folder

b. Run the command below:

/usr/opalrt/common/bin/flash_update -central 0 -remote 1 -safeVC707 /home/ntuser/VC707-EM-0000-SAFE-FFFF-0018.bin

- where 0 is the central Board ID (if different, use the right number);

- where 1 is the remote Board ID (if different, use the right number);

- and where /home/ntuser/VC707-EM-0000-SAFE-FFFF-0018.bin is the exact path of the bitstream 

4) Everything can be validated by following this KB article



VC707-EM-0000-SAFE-FFFF-0018.bin 19.3 Mb 19.3 Mb