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Reference Number: AA-01768// Views: AA-01768// Created: 2019-11-21 21:24:52// Last Updated: 2022-05-19 15:41:56
HowTo
VC707 FPGA not detected - How to Re-Flash a USER Bitstream on a VC707 FPGA Using VIVADO

The SAFE and USER bitstreams are flashed on the FPGA prior to delivery and do not usually need to be re-flashed by the user. However, sometimes it may be necessary to reflash the USER bitstream if it gets corrupted and/or if it is not possible to detect the FPGA anymore. It could also be required in order to use the MUSE feature if the system was shipped prior to 2019. For more details about MUSE, see this KB article.

  

1) Shutdown the simulator

 

2) Connect the simulator to the computer using the USB-B cable

 

3) Power on the simulator and wait a bit for the simulator to boot up and for the computer to detect it


4) Open the Xilinx Vivado software (note that the Vivado Lab Solutions package (lighter) works for this purpose) 


5) Click on Open Hardware Manager


6) Click on Open target and then Auto Connect as shown below:

 



7) The FPGA should appear in the file explorer of the localhost. Right-click on it and select Program Device…



8) In the pop-up window, navigate to the SAFE.bit bitstream to be used (use the *.bit file!) and click OK. You can use the one attached which is also compatible with MUSE.



9) Once the Programming the device... stage is done, the PCIe link between the FPGA and the CPU will be restored. The link between two FPGAs via SFP will be restored as well since this SAFE bitstream is compatible with MUSE.




If programming the FPGA of an expansion chassis connected via SFP using MUSE instead of PCIe, then DO NOT turn off the chassis and continue the procedure in this KB article


Otherwise, if programming the FPGA of a target simulator (with motherboard) or an expansion chassis connected via PCIe to a target simulator (with motherboard), continue to point 10)



10) Reboot the target simulator, with motherboard (either using the reboot command or pressing on the target Reset button, NOT THE power button)


 

11) Use MobaXterm to verify the FPGA is well programmed and now detected via the PCI bus. To do so, simply run the command below where the 0 at the end represents the Board ID (so if the Board ID is different, use the proper number)


/usr/opalrt/common/bin/flash_update -hinfo VC707 0


You can skip this step if you are installing a Hypersim bitstream.


12) At this point, the FPGA has been programmed with the SAFE bitstream via JTAG (*.bit file). Now, re-program the Flash with the USER.bin (the .bin delivered with your system) using the flash_update command (*.bin file). To do so, use MobaXterm and:

For RT-Lab bitstreams:

a. Copy the USER.bin file (the .bin delivered with your system) in the target /home/ntuser/ folder

b. Run the command below (replacing USER-BITSTREAM-NAME with the correct name of the file you placed in the home/ntuser/ folder)

/usr/opalrt/common/bin/flash_update /home/ntuser/USER-BITSTREAM-NAME.bin

c. Everything can be validated by following this KB article

For Hypersim bitstreams:


       a. Copy the Bitstream file (or drag and drop it) to any folder inside the target 


       b. Execute this command: /export/local/ssr//-opalrt/HyServer/bin/flashupdate


To see an example of how this is done for a Hypersim bitstream on CentOS, follow the directions in this KB article



VC707-EM-0000-SAFE-FFFF-001B.bit 19.3 Mb 19.3 Mb