Knowledge Base
Welcome to OPAL-RT’s Knowledge Base
OPAL-RT offers a repository of support information for optimal use of its technology.
Please note that OPAL-RT knowledge base is not fully optimized for mobile platforms.
For optimal experience, use a desktop computer.
Reference Number: AA-01769// Views: AA-01769// Created: 2019-11-21 21:27:19// Last Updated: 2022-02-10 18:33:36 HowTo TE0741 FPGA not detected - How to Re-Flash a USER Bitstream on a TE0741 FPGA Using VIVADO The SAFE and USER bitstream are flashed on the FPGA prior to delivery and does not usually need to be re-flashed by the user. That being said, it can be required to reflash the USER bitstream if it gets corrupted and/or if it is not possible to detect the FPGA anymore. It could also be required in order to use the MUSE feature if the system was shipped prior to 2019. For more details about MUSE, see this KB article. 1) Shutdown
the simulator 2) Connect
the simulator to the computer using the JTAG cable Be careful, the connector has an orientation denoted by a notch. 3) Power
on the simulator and wait a bit for the simulator to boot up and for the computer
to detect the it 4) Open the Xilinx Vivado software (note that the Vivado Lab Solutions package (lighter) works for this purpose) 5) Click on Open Hardware Manager 6) Click on Open target and then Auto Connect has shown below: 7) The FPGA should appear in the file explorer of the localhost. Right-click on it and select Program Device… 8) In the pop-up window, browse for the SAFE.bit bitstream to be used (use the *.bit file!) and click OK. You can use the one attached which is also compatible for MUSE. 9) Once the Programming the device... stage is done, the PCIe link between the FPGA and the CPU will be restored. The link between two FPGAs via SFP will be restored as well since this SAFE bitstream is compatible with MUSE. If programming the FPGA of an expansion chassis, not connected via PCIe but via SFP using MUSE, then DO NOT turn off the chassis and continue the procedure in this KB article Otherwise, if programming the FPGA of a target simulator (with motherboard) or an expansion chassis connected via PCIe to a target simulator (with motherboard), continue to point 10) 10) Reboot the target simulator, with motherboard (either using the reboot command or pressing on the target Reset button, NOT THE power button) 11) Ideally, use MobaXterm and verify the FPGA is well programmed and now detected via the PCI bus. To do so, simply run the command below where the 0 at the end represent the Board ID (so if the Board ID is different, use the proper number) /usr/opalrt/common/bin/flash_update -hinfo TE0741 0 12) At this point, the FPGA has been programmed with the SAFE bitstream via JTAG (*.bit file). Now, re-program the Flash with the USER.bin (the .bin delivered with your system) using the flash_update command (*.bin file).
To do so, use MobaXterm
and: a. Copy the USER.bin file (the .bin delivered with your system) in the target /home/ntuser/ folder b. Run the command below (replacing USER-BITSTREAM-NAME by the correct name of the file you place in the home/ntuser/ folder) /usr/opalrt/common/bin/flash_update /home/ntuser/USER-BITSTREAM-NAME.bin NOTE: If you want to flash a SAFE .bin (and not a user bitstream), you need to add -safeTE0741 after flash_update, i.e.: /usr/opalrt/common/bin/flash_update -safeTE0741 /home/ntuser/SAFE-BITSTREAM-NAME.bin
13) Everything can be validate by following this KB article
|